1. Field of the Invention
The invention relates to an embedded system, more particularly to an embedded system with an instruction prefetch device and to a method for fetching instructions in embedded systems.
2. Description of the Related Art
FIG. 1 illustrates a conventional embedded system 5 that includes a system bus 54, a processor 51 coupled to the system bus 54, a memory controller 52 coupled to the system bus 54, a peripheral controller 53 coupled to the system bus 54, and a memory device 55 coupled to the memory controller 52. The peripheral controller 53 may be various controllers or drivers coupled to the system bus 54 and can be controlled by the processor 51. For example, in a cellular phone applications, the peripheral controller 53 may be a controller to control the LCD or keypad of a cellular phone. When the processor 51 generates an access request for the memory device 55, the memory controller 52 fetches an instruction corresponding to the access request from the processor 51 from the memory device 55, and provides the instruction to the system bus 54 for receipt by the processor 51.
Although the conventional embedded system has a lower system performance, it works well in various applications. However, as the embedded system 5 becomes more complex, the embedded system 5 is required to run at higher speeds to achieve better performance. More particularly, access latency occurs during fetching of an instruction from the memory device 55 after the processor 51 sent out an access request (i.e., fetching cycle), so the performance of the processor 51 is degraded. For the conventional embedded system, the fetching cycle occupies approximately 30%˜50% of the instruction cycle of the processor 51, so access latency is a problem which cannot be ignored.
Two methods are proposed in the art in order to overcome the above problem.
1. An additional cache memory (L2 cache) is incorporated to enhance the embedded system performance. However, the cache memory (such as an SRAM) has a higher cost and a relatively small memory capacity.
2. When the processor 51 executes an instruction, fetching of a next instruction is executed at the same time. However, when the next instruction is among a series of consecutive instructions or has too many branch instructions, data access to or from the peripheral controller 53 must wait until fetching of the next instruction has been completed by the processor 51. FIG. 2 is a timing chart to illustrate an operating example of the conventional embedded system 5. The system bus 54 is occupied by the instruction fetch phase and the data access phase in turns. In the instruction phase, the processor 51 communicates with the memory device 55 and fetches instructions or data stored in the memory device 55; whereas in the data access phase, the processor 51 communicates with the peripheral controller 53 and requests the peripheral controller 53 to perform certain actions. As such, when the system bus 54 is in the data access phase, the memory controller 52 remains idle for a period of time (about two bus cycles) until the data access phase is completed.